3-9 features ? internal control latches and address decoder ? short set-up and hold times ? wide operating voltage: 4.5v to 13.2v ? 12vpp analog signal capability ?r on 65 w max. @ v dd =12v, 25c ? d r on 10 w @ v dd =12v, 25c ? full cmos switch for low distortion ? minimum feedthrough and crosstalk ? separate analog and digital reference supplies ? low power consumption iso-cmos technology applications ? key systems ? pbx systems ? mobile radio ? test equipment/instrumentation ? analog/digital multiplexers ? audio/video switching description the mitel MT8806 is fabricated in mitels iso- cmos technology providing low power dissipation and high reliability. the device contains a 8 x 4 array of crosspoint switches along with a 5 to 32 line decoder and latch circuits. any one of the 32 switches can be addressed by selecting the appropriate five address bits. the selected switch can be turned on or off by applying a logical one or zero to the data input. v ss is the ground reference of the digital inputs. the range of the analog signal is from v dd to v ee . chip select (cs) allows the crosspoint array to be cascaded for matrix expansion. ordering information MT8806ac 24 pin ceramic dip MT8806ae 24 pin plastic dip MT8806ap 28 pin plcc -40 to 85c figure 1 - functional block diagram 5 to 32 decoder latches 8 x 4 switch array ax0 ax1 ay0 ay1 ay2 cs strobe data reset vdd vee vss xi i/o (i=0-3) yi i/o (i=0-7) 11 32 32 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? issue 2 november 1988 MT8806 8 x 4 analog switch array iso-cmos
MT8806 iso-cmos 3-10 figure 2 - pin connections * plastic dip and cerdip only pin description pin #* name description 1-3 y2-y0 y2-y0 analog (inputs/outputs): these are connected to the y2-y0 columns of the switch array. 4data data (input) : a logic high input will turn on the selected switch and a logic low will turn off the selected switch. active high. 5x0 x0 analog (input/output): this is connected to the x0 row of the switch array. 6ax0 x0 address line (input) . 7x1 x1 analog (input/output): this is connected to the x1 row of the switch array. 8ax1 x1 address line (input) . 9x2 x2 analog (input/output): this is connected to the x2 row of the switch array. 10 cs chip select (input) : this is used to select the device. active high. 11 x3 x3 analog (input/output): this is connected to the x3 row of the switch array. 12 v ss digital ground reference. 13 v ee negative power supply. 14-16 ay0-ay2 y0 -y2 address lines (inputs) . 17 strobe strobe (input) : enables function selected by address and data. address must be stable before strobe goes high and data must be stable on the falling edge of the strobe. active high. 18 reset master reset (input): this is used to turn off all switches regardless of the condition of cs. active high. 19-23 y7-y3 y7-y3 analog (inputs/outputs): these are connected to the y7-y3 columns of the switch array. 24 vdd positive power supply. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 y2 y1 y0 data x0 ax0 x1 ax1 x2 cs x3 vss vdd y3 y4 y5 y6 y7 reset strobe ay2 ay1 ay0 vee 28 pin plcc 24 pin cerdip/plastic dip 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 n c y5 y6 y7 reset strobe ay2 nc nc d0 j0 d1 j1 d2 j2 a y 1 3 2 1 2 8 2 7 2 6 1 2 1 3 1 4 1 5 1 6 1 7 1 8 y 0 y 1 y 2 v d d y 3 y 4 c s x 3 v s s v e e a y 0 n c
iso-cmos MT8806 3-11 functional description the MT8806 is an analog switch matrix with an array size of 8 x 4. the switch array is arranged such that there are 8 columns by 4 rows. the columns are referred to as the y inputs/outputs and the rows are the x inputs/outputs. the crosspoint analog switch array will interconnect any x i/o with any y i/o when turned on and provide a high degree of isolation when turned off. the control memory consists of a 32 bit write only ram in which the bits are selected by the address inputs (ay0-ay2, ax0 & ax1). data is presented to the memory on the data input. data is asynchronously written into memory whenever both the cs (chip select) and the strobe inputs are high and is latched on the falling edge of strobe. a logical 1 written into a memory cell turns the corresponding crosspoint switch on and a logical 0 turns the crosspoint off. only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. the remaining switches retain their previous states. any combination of x and y inputs/ outputs can be interconnected by establishing appropriate patterns in the control memory. a logical 1 on the reset input will asynchronously return all memory locations to logical 0 turning off all crosspoint switches regardless of whether cs is high or low. two voltage reference pins (v ss and v ee ) are provided for the MT8806 to enable switching of negative analog signals. the range for digital signals is from v dd to v ss while the range for analog signals is from v dd to v ee . v ss and v ee pins can be tied together if a single voltage reference is needed. address decode the five address inputs along with the strobe and cs (chip select) inputs are logically anded to form an enable signal for the resettable transparent latches. the data input is buffered and is used as the input to all latches. to write to a location, reset must be low and cs must go high while the address and data are set up. then the strobe input is set high and then low causing the data to be latched. the data can be changed while strobe is high, however, the corresponding switch will turn on and off in accordance with the data input. data must be stable on the falling edge of strobe in order for correct data to be written to the latch.
MT8806 iso-cmos 3-12 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? dc electrical characteristics are over recommended temperature range. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing. absolute maximum ratings * - voltages are with respect to v ee unless otherwise stated. parameter symbol min max units 1 supply voltage v dd v ss -0.3 -0.3 15.0 v dd +0.3 v v 2 analog input voltage v ina -0.3 v dd +0.3 v 3 digital input voltage v in v ss -0.3 v dd +0.3 v 4 current on any i/o pin i 15 ma 5 storage temperature t s -65 +150 c 6 package power dissipation plastic dip cerdip p d p d 0.6 1.0 w w recommended operating conditions - voltages are with respect to v ee unless otherwise stated. characteristics sym min typ max units test conditions 1 operating temperature t o -40 25 85 c 2 supply voltage v dd v ss 4.5 v ee 13.2 v dd -4.5 v v 3 analog input voltage v ina v ee v dd v 4 digital input voltage v in v ss v dd v dc electrical characteristics ? - voltages are with respect to v ee =v ss =0v, v dd =12v unless otherwise stated. characteristics sym min typ ? max units test conditions 1 quiescent supply current i dd 1100 a all digital inputs at v in =v ss or v dd 0.4 1.5 ma all digital inputs at v in =2.4 + v ss ; v ss =7.0v 5 15 ma all digital inputs at v in =3.4v 2 off-state leakage current (see g.9 in appendix) i off 1 500 na iv xi - v yj i = v dd - v ee see appendix, fig. a.1 3 input logic 0 level v il 0.8+v s s vv ss =7.5v; v ee =0v 4 input logic 1 level v ih 2.0+v ss vv ss =6.5v; v ee =0v 5 input logic 1 level v ih 3.3 v 6 input leakage (digital pins) i leak 0.1 10 a all digital inputs at v in = v ss or v dd dc electrical characteristics- switch resistance - v dc is the external dc offset applied at the analog i/o pins. characteristics sym 25c 70c 85c units test conditions typ max typ max typ max 1 on-state v dd =12v resistance v dd =10v v dd = 5v (see g.1, g.2, g.3 in appendix) r on 45 55 120 65 75 185 75 85 215 80 90 225 w w w v ss =v ee =0v,v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2 2 difference in on-state resistance between two switches (see g.4 in appendix) d r on 510 10 10 w v dd =12v, v ss =v ee =0, v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2
iso-cmos MT8806 3-13 ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing. crosstalk measurements are for plastic dips only, crosstalk values for plcc packages are approximately 5db better. ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. digital input rise time (tr) and fall time (tf) = 5ns. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing. ? refer to appendix, fig. a.7 for test circuit. ac electrical characteristics ? - crosspoint performance - voltages are with respect to v dd =5v, v ss =0v, v ee =-7v, unless otherwise stated. characteristics sym min typ ? max units test conditions 1 switch i/o capacitance c s 20 pf f=1 mhz 2 feedthrough capacitance c f 0.2 pf f=1 mhz 3 frequency response channel on 20log(v out /v xi )=-3db f 3db 45 mhz switch is on; v ina = 2vpp sinewave; r l = 1k w see appendix, fig. a.3 4 total harmonic distortion (see g.5, g.6 in appendix) thd 0.01 % switch is on; v ina = 2vpp sinewave f= 1khz ; r l =1k w 5 feedthrough channel off feed.=20log (v out /v xi ) (see g.8 in appendix) fdt -95 db all switches off; v ina = 2vpp sinewave; f= 1khz; r l = 1k w . see appendix, fig. a.4 6 crosstalk between any two channels for switches xi-yi and xj-yj. xtalk=20log (v yj /v xi ). (see g.7 in appendix). x talk -45 db v ina =2vpp sinewave f= 10mhz; r l = 75 w . -90 db v ina =2vpp sinewave f= 10khz; r l = 600 w . -85 db v ina =2vpp sinewave f= 10khz; r l = 1k w . -80 db v ina =2vpp sinewave f= 1khz; r l = 10k w . refer to appendix, fig. a.5 for test circuit. 7 propagation delay through switch t ps 30 ns r l =1k w ; c l =50pf ac electrical characteristics ? - control and i/o timings - voltages are with respect to v dd =5v, v ss =0v, v ee =-7v, unless otherwise stated. characteristics sym min typ ? max units test conditions 1 control input crosstalk to switch (for cs, data, strobe, address) cx talk 30 mvpp v in =3v squarewave; r in =1k w , r l =10k w . see appendix, fig. a.6 2 digital input capacitance c di 10 pf f=1mhz 3 switching frequency f o 20 mhz 4 setup time data to strobe t ds 10 ns r l = 1k w , c l =50pf ? 5 hold time data to strobe t dh 10 ns r l = 1k w , c l =50pf ? 6 setup time address to strobe t as 10 ns r l = 1k w , c l =50pf ? 7 hold time address to strobe t ah 10 ns r l = 1k w , c l =50pf ? 8 setup time cs to strobe t css 10 ns r l = 1k w , c l =50pf ? 9 hold time cs to strobe t csh 10 ns r l = 1k w , c l =50pf ? 10 strobe pulse width t spw 20 ns r l = 1k w , c l =50pf ? 11 reset pulse width t rpw 40 ns r l = 1k w , c l =50pf ? 12 strobe to switch status delay t s 40 100 ns r l = 1k w , c l =50pf ? 13 data to switch status delay t d 50 100 ns r l = 1k w , c l =50pf ? 14 reset to switch status delay t r 35 100 ns r l = 1k w , c l =50pf ?
MT8806 iso-cmos 3-14 figure 3 - control memory timing diagram * see appendix, fig. a.7 for switching waveform table 1. address decode truth table ax0 ax1 ay0 ay1 ay2 connection 0 0 0 0 0 x0-y0 0 0 1 0 0 x0-y1 0 0 0 1 0 x0-y2 0 0 1 1 0 x0-y3 0 0 0 0 1 x0-y4 0 0 1 0 1 x0-y5 0 0 0 1 1 x0-y6 0 0 1 1 1 x0-y7 1 1 0 0 0 1 0 1 0 1 x1-y0 x1-y7 0 0 1 1 0 1 0 1 0 1 x2-y0 x2-y7 1 1 1 1 0 1 0 1 0 1 x3-y0 x3-y7 t css t csh t rpw t spw t as t ah t dh t d t s t r t r t ds 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% cs reset strobe address data switch* on off
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